How do you optimize test program efficiency without compromising quality? Every semiconductor test facility has a budget for how much time it can dedicate to any given testing menu, making the introduction of TTR programs an inevitable reality – and raising equally inevitable questions as to the ultimate quality of the tested parts.

Optimal+ TTR is an IIoT-ready solution that enables you to leverage the potentially damaging constraints of limited test time to actually increase quality, not reduce it. Rather than just removing a so-called “no-fail” test permanently from a testing program, TTR turns it on/off at designated intervals so that if there is a manufacturing variation where the test in question does return a fail, you can quickly re-introduce it, effectively boosting quality.

Moreover, using TTR, lengthy tests that are typically removed because they are costly to perform – such as measuring the max speed range of a CPU – can be automatically reintroduced at pre-determined intervals in order to verify that quality and performance assumptions are correct.

Optimal+ Test Time Reduction (TTR) is applicable for use by internal operations (IDMs) or across globally dispersed operations (Fabless).

Reduced Time, Augmented Quality

The Optimal+ TTR solution reduces test time by as much as 30% without compromising quality, yield or reliability

Adaptive & Agile Testing

Optimal+ TTR combines traditional test time reduction techniques with innovative implementation of intelligent adaptive testing in an entirely automated process throughout the IC lifecycle.

Centralized Tracking

The solution tracks the state of your global TTR activities from a single central location and automatically publishes new test programs rules across your supply chain, driving quality and improving efficiencies.

Ensures Test Validity

The Optimal+ TTR solutions ensures the validity of your TTR recipes by analyzing and simulating TTR rules using historical product data, including the periodic re-introduction of expensive and “no-fail” tests in order to detect potential failures and increase quality.


The Optimal+ Semiconductor Operations Platform Workflow

Our solutions are installed in 90% of the foundries and subcons serving the global semiconductor industry, enabling IDM and fabless teams to seamlessly collect, clean and collate their data sets directly from the source of their creation in preparation for extreme analytics and time-sensitive action. The data then goes through a multi-stage process that enables teams to manufacture actionable intelligence that drives every quantifiable performance metric, as described in the diagram below:


Driving Test Time Reduction with Adaptive Test

The Issue
Lot-to-Lot variability provides many opportunities to reduce test time without impacting quality.

Performing the Analysis
Across multiple lots, the overall yield and quality of a device can vary widely. By creating baselines of individual and group tests, the Optimal+ TTR solution can analyze both parametric as well as go/no-go tests to find opportunities to apply adaptive test algorithms that can reduce test time by up to 30%. Intelligent algorithms can also track statistical trend data for parametric values to dynamically adjust or stop sampling based on user-defined upper and lower estimating limits.



Using TTR simulation to initiate safe and accurate adaptive test

The Issue
Enabling teams to quickly determine which tests are the best potential candidates for adaptive test.

Performing the Analysis
The Optimal+ Test Time Reduction (TTR) solution includes a powerful simulation engine that creates precise scenarios of what occurs during production. TTR automatically analyzes all tests and identifies the best test candidates on which to apply adaptive test that will drive the maximum test time reduction and simultaneously avoid test escapes.

TTR simulation results