Having seen the analytic results on literally billions of devices that have been tested across the industry, Optimal+ knows what separates quality products from tomorrow’s RMAs. 

Our production-proven IIoT solutions for escape prevention and outlier detection deliver a powerful combination of deterministic and statistical analytic capabilities that are unsurpassed in helping you provide your customers with the highest quality products with the lowest defect rates.

Manufacturing intelligence to ensure Quality:

Automated Escape Prevention Rules

Optimal+ gives you proven, automated test solutions that improve test process stability and transparency through advanced data integrity checks. These rules virtually eliminate human error and increase overall quality.

RMA Database

The Optimal+ database provides detailed information about customer RMAs and contains a customizable interface that enables unprecedented historical analysis. All of our product analytic capabilities can subsequently be applied to quickly determine the root causes of the failure.

Quality Index

Using powerful cross-operational analysis capabilities, Optimal+ generates a Quality Index that enables operations teams to perform highly-sophisticated binning by tracking multiple device parameters across multiple test phases.

Outlier Detection

Optimal+ provides numerous quality rules in our Outlier Detection solution to drive higher quality through analysis of good bins. A number of production-proven parametric and geographic algorithms are available to detect outliers. These algorithms can also be combined and executed either on single or multiple operations.

Statistical Process Control (SPC)

Optimal+ IIoT solutions can dramatically improve your test process quality through a rich, unique selection of algorithms and methodologies, both in real-time and offline, as well as through early detection, helping to ensure maximum quality values are achieved.

“With Optimal+ we can make very sophisticated real-time decisions that enable us to measurably improve our product quality”


Craig Nishizaki

Senior Director of ATE Development,
NVIDIA

Examples

Detecting Parametric Test Freezes

Finding the Issue
An Optimal+ real-time parametric freeze rule detects a “frozen” test where similar values are being reported for a sequence of parts.

Performing the Analysis
After receiving the alert, the product and test engineer view the lot’s trend chart in the Optimal+ solution’s portal where the freeze is clearly visible. Since this is a quality issue with potential test escapes, the lot is retested.

A

img_2 Detecting Parametric Test Freezes

Improving Quality by Catching Linear Degradation of Tests

Finding the Issue
An Optimal+ online parametric trend rule detects a linear degradation in test results of a specific test on a specific test site.

Performing the Analysis
When the alert is received, the user opens the Optimal+ solution portal to view a detailed trend plot of the offending test site. Due to the nature of the issue, it is assumed that the test results of the devices tested under the suspected site are unreliable resulting in a potential quality issue. The parts are retested on another tester and the loadboard is serviced.

linear-degradation

Improving_Quality_by_Catching_Linear_Degradation_of_Tests

 

img_2 Improving Quality by Catching Linear Degradation of Tests

Uncovering Geographic Issues at Final Test

Finding the Issue
When a chip has an Electronic Chip ID (ECID) it is possible to discover wafer geography issues based on final test data. Even though parts pass at wafer sort, they fail at final test and the fallout is related to wafer geography and fab process issues. The trigger for performing this analysis is a final test parametric test that has a higher than expected failure rate. This is discovered using a failing test Pareto chart in the Optimal+ solution’s portal.

Performing the Analysis
In this example, an engineer uses the solution’s wafer map reconstruction capabilities to analyze the fallout of a parametric test performed at final test. Wafer map reconstruction is an excellent tool for yield learning analysis. The wafer clearly shows that most of the failures occur near the edge of the wafer. The impact of this issue is that failures, which could be detected at wafer sort, were deferred to final test, causing costly and unnecessary packaging of bad devices.

This issue is resolved by creating a screening test in the wafer sort process so that these problems are caught earlier. The fab is notified so that improvements can be made to the wafer manufacturing process. We call this useful capability “Data Feed Backward” – taking data from a later operation and using it for yield learning in earlier operations.

 

data-feed

img_2 Uncovering Geographic Issues at Final Test